An Efficient FPGA-Based Turbo Decoder and Its Application in FH-SS System

This paper focuses on implementing an efficient and simplified turbo decoder with FPGA. The Max-Log-MAP algorithm is employed and a simplified and improved Max-Log- MAP algorithm is present. By carefully manipulating hardware, we implement the whole turbo decoder with a single-RSC structure. Comparing with the conventional decoder, our turbo decoder reduces about 60% hardware cost and operates up to 2Mbit/s. Finally, we investigate the performance of our FPGA-based turbo decoder in a FH-SS system with partial band jamming. The results drawn from this code are compared with a RS code. Results show that the turbo code significantly outperforms the RS code.