Dual and fail-safe redundancy for static mask-ROMs and PLAs

An advanced dual and fail-safe redundancy configuration for static mask-ROMs is presented. This configuration uses double coding-point cells and makes the ROM units more fail-safe by using additional fault-detection circuits. An expanded application of the proposed redundancy scheme to programmable logic arrays (PLAs) consisting of AND-ROM and OR-ROM pairs is proposed. If applied to a 256-kb ROM and a 49-k program-point PLA using 1.5- mu m CMOS technology, it is estimated that the proposed redundancy reduces the effective circuit area for defect occurrence to 16% of that of the nonredundant basic circuit module for the ROM, and to 9% for the PLA.