Title :
Dual and fail-safe redundancy for static mask-ROMs and PLAs
Author_Institution :
NTT Network Inf. Syst. Lab., Tokyo, Japan
Abstract :
An advanced dual and fail-safe redundancy configuration for static mask-ROMs is presented. This configuration uses double coding-point cells and makes the ROM units more fail-safe by using additional fault-detection circuits. An expanded application of the proposed redundancy scheme to programmable logic arrays (PLAs) consisting of AND-ROM and OR-ROM pairs is proposed. If applied to a 256-kb ROM and a 49-k program-point PLA using 1.5- mu m CMOS technology, it is estimated that the proposed redundancy reduces the effective circuit area for defect occurrence to 16% of that of the nonredundant basic circuit module for the ROM, and to 9% for the PLA.
Keywords :
CMOS integrated circuits; logic arrays; read-only storage; redundancy; 1.5 micron; 256 Kbit; AND-ROM pairs; CMOS technology; OR-ROM pairs; PLAs; ROMs; defect occurrence; double coding-point cells; effective circuit area; fail-safe redundancy; fault-detection circuits; static mask; Automatic control; CMOS technology; Circuit faults; Information systems; Laboratories; Programmable logic arrays; Read only memory; Redundancy; Storage automation; Very large scale integration;
Conference_Titel :
Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0867-0
DOI :
10.1109/ICWSI.1993.255273