Title :
Architectures for catastrophic and delay fault tolerance
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
Wafer-scale architectures have defect tolerance as one of their primary goals. Anecdotal data and simulation experiments indicate that as geometries shrink, delay faults caused by spot defects will become increasingly important, and must be tolerated in order for wafer-scale architectures to have acceptable parametric yield. Approaches to designing architectures that possess both catastrophic and delay fault tolerance are presented.
Keywords :
CMOS integrated circuits; SRAM chips; VLSI; fault tolerant computing; logic arrays; parallel architectures; CMOS; catastrophic fault tolerance; delay fault tolerance; parametric yield; spot defects; wafer-scale architectures; CMOS technology; Circuit faults; Clocks; Computer architecture; Delay estimation; Fault tolerance; Frequency; Geometry; Manufacturing processes; Propagation delay;
Conference_Titel :
Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0867-0
DOI :
10.1109/ICWSI.1993.255274