Title :
A full experience of designing a wafer scale 2D array
Author :
Boubekeur, A. ; Patry, J.L. ; Saucier, G. ; Slimane-kadi, M. ; Trilhe, J.
Author_Institution :
Inst. Nat. Polytech. de Grenoble, France
Abstract :
The design of a wafer scale 2D array called ELSA (European large single instruction, multiple data (SIMD) array) is given. Software methods and tools as well as hardware switching devices used to achieve defect tolerance and create a defect-free 2D array are described. ELSA is implemented in 1.2- mu m CMOS technology and has been studied within an ESPRIT project on wafer scale integration.
Keywords :
CMOS integrated circuits; VLSI; parallel architectures; systolic arrays; 1.2 micron; CMOS technology; ELSA; European large SIMD array; defect tolerance; hardware switching devices; software tools; wafer scale 2D array; wafer scale integration; CMOS technology; Hardware; Manufacturing; Proposals; Read-write memory; Registers; Software tools; Switches; Testing; Wafer scale integration;
Conference_Titel :
Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0867-0
DOI :
10.1109/ICWSI.1993.255275
