Title :
Silicon-on-insulator `gate-all-around´ MOS device
Author :
Colinge, J.-P. ; Gao, M.H. ; Romano, A. ; Maes, H. ; Claeys, C.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
The total-dose radiation hardness of MOS devices is roughly inversely proportional to the square of the thickness of the oxide layers in contact with the silicon. In SOI (silicon-on-insulator) devices, the silicon layer sits on an oxide layer of typically 400 nm. It is proposed that a thin, gate-quality oxide can be realized at the front as well as the back of the devices, which should greatly enhance the radiation hardness. Double-gate devices (i.e. the same gate at the front and the back of the device) have been shown to have, at least theoretically, interesting short-channel and high transconductance properties. The only reported realization of such a device used a complicated, highly non-planar process (vertical devices) and left one edge of the device in contact with a thick oxide, which can be detrimental to rad-hard performances. Fabrication processes and device performances are described
Keywords :
insulated gate field effect transistors; metal-insulator-semiconductor devices; radiation hardening (electronics); semiconductor-insulator boundaries; 400 nm; MOS devices; SOI; Si-SiO2; device performances; double gate devices; fabrication; gate-quality oxide; high transconductance; nonplanar process; short-channel; silicon-on-insulator; total-dose radiation hardness; vertical devices; Bridge circuits; Electron devices; MOS devices; MOSFET circuits; Radiation hardening; Semiconductor films; Silicon on insulator technology; Threshold voltage; Transconductance; Wet etching;
Conference_Titel :
SOS/SOI Technology Conference, 1990., 1990 IEEE
Conference_Location :
Key West, FL
Print_ISBN :
0-87942-573-3
DOI :
10.1109/SOSSOI.1990.145749