Title :
A glitch-corrector circuit for low-spur ADPLLs
Author :
Zanuso, M. ; Levantino, S. ; Tasca, D. ; Raiteri, D. ; Samori, C. ; Lacaita, A.L.
Author_Institution :
Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
Abstract :
This paper analyzes the effect of the time skew between counter and TDC inputs in the generation of spurious tones in the output spectrum of an all-digital PLL (AD-PLL) and proposes a simple glitch-removal circuit, capable of operating even in the presence of fast and large frequency drifts. This technique is applied to the design of a 90-nm CMOS AD-PLL operating in the 3-4-GHz band. The frequency and the level of the main spur with the time skew but without the glitch corrector are first analytically estimated and then confirmed by simulations. The glitch corrector is demonstrated to cancel out the -24-dBc spur and its harmonics, without altering the lock transient behavior.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; field effect MMIC; CMOS AD-PLL; frequency 3 GHz to 4 GHz; glitch-corrector circuit; low-spur all-digital PLL; size 90 nm; Adders; Analytical models; Circuit topology; Counting circuits; Digital filters; Electronic mail; Frequency estimation; Microelectronics; Phase locked loops; Power harmonic filters;
Conference_Titel :
Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on
Conference_Location :
Yasmine Hammamet
Print_ISBN :
978-1-4244-5090-9
Electronic_ISBN :
978-1-4244-5091-6
DOI :
10.1109/ICECS.2009.5410853