A glitch-corrector circuit for low-spur ADPLLs

This paper analyzes the effect of the time skew between counter and TDC inputs in the generation of spurious tones in the output spectrum of an all-digital PLL (AD-PLL) and proposes a simple glitch-removal circuit, capable of operating even in the presence of fast and large frequency drifts. This technique is applied to the design of a 90-nm CMOS AD-PLL operating in the 3-4-GHz band. The frequency and the level of the main spur with the time skew but without the glitch corrector are first analytically estimated and then confirmed by simulations. The glitch corrector is demonstrated to cancel out the -24-dBc spur and its harmonics, without altering the lock transient behavior.