• DocumentCode
    3434927
  • Title

    Interface timing verification with delay correlation using constraint logic programming

  • Author

    Girodias, Pierre ; Cerny, Eduard

  • Author_Institution
    Dept. d´´Inf. et de Recherche Oper., Montreal Univ., Que., Canada
  • fYear
    1997
  • fDate
    17-20 Mar 1997
  • Firstpage
    12
  • Lastpage
    19
  • Abstract
    Using constraint logic programming and relational interval arithmetic, as implemented in CLP (BNR) Prolog, we develop a simple yet complete method for interface timing verification. We show how the problems raised by timing verification (consistency, causality and compatibility) can be formulated as constraint satisfaction problems and solved using relational interval arithmetic when the timing constraints are of the linear, earliest or latest type; we examine the effect of correlation between timing delays (within their specified intervals) and show how an interval delay narrowing method can be applied in this context. The original contribution of this paper is to provide a unifying framework for interface timing verification and to present a method that allows delay correlation to be considered
  • Keywords
    PROLOG; computer interfaces; constraint handling; correlation methods; delays; formal verification; timing; CLP (BNR) Prolog; causality; compatibility; consistency; constraint logic programming; delay correlation; interface timing verification; relational interval arithmetic; satisfiability; Arithmetic; Delay; Hardware; Logic programming; Protocols; Read-write memory; Testing; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    European Design and Test Conference, 1997. ED&TC 97. Proceedings
  • Conference_Location
    Paris
  • ISSN
    1066-1409
  • Print_ISBN
    0-8186-7786-4
  • Type

    conf

  • DOI
    10.1109/EDTC.1997.582324
  • Filename
    582324