• DocumentCode
    3434949
  • Title

    Sequential circuit test generation using dynamic state traversal

  • Author

    Hsiao, Michael S. ; Rudnick, Elizabeth M. ; Patel, Janak H.

  • Author_Institution
    Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
  • fYear
    1997
  • fDate
    17-20 Mar 1997
  • Firstpage
    22
  • Lastpage
    28
  • Abstract
    A new method for state justification is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state justification. State-transfer sequences may already be known that drive the circuit from the current state to the target state. Otherwise, genetic engineering of existing state-transfer sequences is required. In both cases, genetic-algorithm-based techniques are used to generate valid state justification sequences for the circuit in the presence of the target fault. This approach achieves extremely high fault coverages and thus outperforms previous deterministic and simulation-based techniques
  • Keywords
    automatic testing; genetic algorithms; logic testing; sequential circuits; dynamic state traversal; fault coverage; genetic algorithm; linear list; sequential circuit test generation; state justification sequence; Automatic testing; Boolean functions; Circuit faults; Circuit testing; Contracts; Data structures; Electrical fault detection; Flip-flops; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    European Design and Test Conference, 1997. ED&TC 97. Proceedings
  • Conference_Location
    Paris
  • ISSN
    1066-1409
  • Print_ISBN
    0-8186-7786-4
  • Type

    conf

  • DOI
    10.1109/EDTC.1997.582325
  • Filename
    582325