Title :
A FPGA design of the I/Q signal combining for UHF RFID reader receiver
Author :
Kim, Sang Kyu ; Nam, Sung Sik ; Cho, Sung Ho
Author_Institution :
Dept. of Electron. & Comput. Eng., Hanyang Univ., Seoul, South Korea
Abstract :
In this paper, a implementation of the I/Q signal combining for Ultra High Frequency (UHF) Radio Frequency Identification (RFID) reader receiver is presented. The design is concentrated on the low complexity and the low coast of the RFID reader. To reduce the complexity, area consumption and calculation time, the Loop Up Table (LUT) is applied. Only one multiplier and one divider which have many gates size is used for the low cost. The FPGA NCsim simulator is used to verify this design and it is tested on the reader platform based on FPGA. The simulation, design results and the performance results of the reader receiver using the I/Q signal combining is presented.
Keywords :
UHF antennas; field programmable gate arrays; radio receivers; radiofrequency identification; signal processing; table lookup; FPGA NCsim simulator; I/Q signal combining; UHF RFID reader receiver; gate size; lookup table; ultra high frequency radio frequency identification reader receiver; Algorithm design and analysis; Complexity theory; Diversity reception; Field programmable gate arrays; Radiofrequency identification; Receivers; Table lookup; FPGA; I/Q signal combining; RFID;
Conference_Titel :
Network Infrastructure and Digital Content, 2010 2nd IEEE International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-6851-5
DOI :
10.1109/ICNIDC.2010.5657831
