New static compaction techniques of test sequences for sequential circuits

Author

Corno, F. ; Prinetto, P. ; Rebaudengo, M. ; Reorda, M. Soma

Author_Institution

Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

fYear

1997

fDate

17-20 Mar 1997

Firstpage

37

Lastpage

43

Abstract

This paper describes an algorithm for compacting the Test Sequences generated by an ATPG tool without reducing the number of faults they detect. The algorithm is based on re-ordering the sequences so that some of them can be shortened and some others eliminated. The problem is NP-complete, and we adopt Genetic Algorithms to obtain optimal solutions with acceptable computational requirements. As it requires just one preliminary Fault Simulation experiment, the approach is much more efficient than others proposed before; experimental results gathered with Test Sets generated by different ATPG tools show that the method is able to reduce the size of the Test Set by a factor varying between 50% and 62%

Keywords

automatic testing; genetic algorithms; logic testing; sequential circuits; ATPG tool; NP-complete problem; fault detection; fault simulation; genetic algorithm; sequential circuit; static compaction; test sequence; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Compaction; Computational modeling; Genetic algorithms; Sequential analysis; Sequential circuits; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1997. ED&TC 97. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7786-4

Type

conf

DOI

10.1109/EDTC.1997.582327

Filename

582327