Design of low voltage CMOS circuits

Author

Roy, Kaushik ; Krishnammthy, R.

Author_Institution

Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2001

fDate

2001

Abstract

This article discusses high performance and low-power circuits. It covers leakage control (CAD and circuit techniques) including stacked CMOS with gated-Vdd (application: DRI-cache), multiple VT and dynamic VT, circuit techniques (MTCMOS, VTCMOS. DTMOS, SCMOS, etc.) and SOI implementation. Ultra low voltage digital sub-threshold logic in bursty and non-bursty modes for medical applications, and testing of deep sub-micron low voltage CMOS (modified IDDQ testing and cross-talk faults in high speed circuits) are also discussed

Keywords

CMOS integrated circuits; integrated circuit design; low-power electronics; SOI circuit; circuit techniques; deep-sub-micron IC testing; leakage control; low-power circuit; low-voltage CMOS circuit design; ultra-low-voltage digital sub-threshold logic; Biomedical equipment; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Circuit testing; Design automation; Logic testing; Low voltage; Medical services; Medical tests;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. Tutorial Guide: ISCAS 2001. The IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-7113-5

Type

conf

DOI

10.1109/TUTCAS.2001.946950

Filename

946950

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3435053