DocumentCode
3435113
Title
Program disturbs and process optimization in a 65 nm Flash FPGA
Author
Jia, J.Y. ; Singaraju, Pavan ; Micael, H. ; Liu, Peng ; Sammie, S. ; Dhaoui, Fethi ; Hawley, Frank ; Chi Ren ; Zhi Guo Li ; Boon Keat Toh ; Zhao Bing Li ; Tzu-Yun Chang ; Jing Horng Gau ; Yau Kae Sheu
Author_Institution
Microsemi Corp., San Jose, CA, USA
fYear
2012
fDate
14-18 Oct. 2012
Firstpage
117
Lastpage
118
Abstract
We present studies of an extrinsic program disturb mechanism in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. It is concluded that multiple positive charges are involved during disturb to explain the observed extrinsic behavior. Its failure rate was improved with tunnel oxidation process tuning and stronger pre-oxidation cleans.
Keywords
circuit optimisation; circuit tuning; failure analysis; field programmable gate arrays; oxidation; embedded-flash process; extrinsic program disturb mechanism; failure rate; field programmable gate array; flash FPGA; multiple positive charges; observed extrinsic behavior; preoxidation cleans; process optimization; size 65 nm; tunnel oxidation process tuning; Arrays; Field programmable gate arrays; Logic gates; Optimization; Programming; Silicon; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report (IRW), 2012 IEEE International
Conference_Location
South Lake Tahoe, CA
ISSN
1930-8841
Print_ISBN
978-1-4673-2749-7
Type
conf
DOI
10.1109/IIRW.2012.6468933
Filename
6468933
Link To Document