Title :
Structural BIST insertion using behavioral test analysis
Author :
Nourani, M. ; Papachristou, C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
Abstract :
The purpose of this work is to develop a test synthesis technique based on BIST methodology which uses the test metrics (i.e. controllability and observability) obtained by test analysis of the behavior to enhance the testability quality (fault coverage) of the corresponding structure and obtain the scheduled test behavior accordingly. The key feature of this work is in using the Structured Data Flow Graph (SDG) which annotates the behavioral information (e.g. data dependency) and structural information (e.g. binding, connectivity). To enhance testability of the structure, the SDG is modified using transformation technique to improve the fault coverage and shorten the test schedule
Keywords :
built-in self test; circuit CAD; circuit analysis computing; controllability; data flow graphs; design for testability; integrated circuit design; integrated circuit testing; observability; behavioral information; behavioral test analysis; binding; connectivity; controllability; data dependency; fault coverage; observability; scheduled test behavior; structural BIST insertion; structural information; structured DFG; structured data flow graph; test metrics; test synthesis technique; testability enhancement; transformation technique; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Controllability; Design for testability; Entropy; Flow graphs; Libraries; Observability;
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7786-4
DOI :
10.1109/EDTC.1997.582333