DocumentCode
3435269
Title
SpecC design environment
Author
Gajski, Daniel D.
Author_Institution
Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
fYear
2001
fDate
2001
Abstract
The author discusses the SpecC design environment, considering the following topics: validation levels; abstraction levels; SpecC scope, methodology and refinements; refinement user interface; user feedback; user guided refinement; automatic refinement; validation user interface; modelling, refinement, exploration and synthesis engines
Keywords
circuit CAD; circuit layout CAD; high level synthesis; integrated circuit design; user interfaces; SpecC design environment; abstraction levels; automatic refinement; exploration engine; modelling engine; refinement engine; refinement user interface; synthesis engine; user guided refinement; validation levels; validation user interface; Design methodology;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. Tutorial Guide: ISCAS 2001. The IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-7113-5
Type
conf
DOI
10.1109/TUTCAS.2001.946963
Filename
946963
Link To Document