• DocumentCode
    3435503
  • Title

    Two-point capacitance-voltage (TPCV) concept: A new method for NBTI characterization

  • Author

    Benabdelmoumene, Abdelmadjid ; Djezzar, Boualem ; Tahi, Hakim ; Chenouf, Amel ; Trombetta, L. ; Kechouane, Mohamed

  • Author_Institution
    Microelectron. & Nanotechnol. Div., Centre de Dev. des Technol. Av., Baba Hassen, Algeria
  • fYear
    2012
  • fDate
    14-18 Oct. 2012
  • Firstpage
    175
  • Lastpage
    178
  • Abstract
    Negative bias temperature instability (NBTI) in MOS capacitors has been investigated using a novel NBTI measurement method, named two-point capacitance-voltage (TPCV). This method is based on C-V techniques and allows one to independently separate the interface (ΔNit) and oxide traps (ΔNot) induced by NBTI. For the first time, to our knowledge, such a method is proposed. The TPCV method permits a broad investigation in reliability studies by exploiting changes in capacitance. It is based on a simple theoretical concept and consists of measuring the evolution of capacitance at two points; the first at the flat-band voltage (Vfb) and the second at Vfb + ΔV. By assuming a linear CV characteristic variation between Vfb and mid-gap voltage (Vmg), the relations of voltage shifts components (Vfb, Vmg, and Vit) are developed. The experimental results have shown that the proposed approach allows reducing the recovery amount compared to full CV characteristics. The trapped charge, ΔNot and ΔNit present a power law stress-time-dependence. In addition, the results have shown a quasi different kinetic of interface state generation as well as oxide trapped charges, while the component ΔNot is greater than ΔNit.
  • Keywords
    MOS capacitors; interface states; reliability; temperature measurement; C-V techniques; MOS capacitors; NBTI characterization; NBTI measurement method; TPCV concept; flat-band voltage; interface state generation; linear CV characteristic variation; mid-gap voltage; negative bias temperature instability; oxide trapped charges; oxide traps; power law stress-time-dependence; reliability study; two-point capacitance-voltage concept; voltage shift components; Capacitance; Degradation; Logic gates; MOS capacitors; Reliability; Stress; Temperature measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Reliability Workshop Final Report (IRW), 2012 IEEE International
  • Conference_Location
    South Lake Tahoe, CA
  • ISSN
    1930-8841
  • Print_ISBN
    978-1-4673-2749-7
  • Type

    conf

  • DOI
    10.1109/IIRW.2012.6468949
  • Filename
    6468949