Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies

Author

Tekfouy Lim ; Jimenez, Joaquin ; Benech, Ph ; Fournier, Jacques ; Heitz, B. ; Galy, Ph

Author_Institution

STMicroelectron., Crolles, France

fYear

2012

fDate

14-18 Oct. 2012

Firstpage

183

Lastpage

186

Abstract

Advanced CMOS technologies provide an easy way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharge (ESD) issues become more significant. Unfortunately, parasitic capacitance of the ESD protection limits the operating bandwidth of the RFICs. The size (i.e. die area) of ESD protection is also of concern in RFICs. This paper presents results of transmission line with ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies.

Keywords

CMOS integrated circuits; electrostatic discharge; radiofrequency integrated circuits; transmission lines; ESD protection devices; I/O pad; RF performances; RFIC; advanced CMOS technology; broadband ESD self-protected transmission line; electrostatic discharge; radiofrequency integrated circuits; transistor gates; Broadband communication; CMOS integrated circuits; CMOS technology; Electrostatic discharges; Impedance; Radio frequency; Transmission line measurements;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report (IRW), 2012 IEEE International

Conference_Location

South Lake Tahoe, CA

ISSN

1930-8841

Print_ISBN

978-1-4673-2749-7

Type

conf

DOI

10.1109/IIRW.2012.6468951

Filename

6468951