Wave-pipelining: is it practical?

Author

Burleston, W. ; Cotton, L.W. ; Klaus, F. ; Ciesielski, Maciej

Author_Institution

Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA

Volume

4

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

163

Abstract

Wave-pipelining has recently drawn considerable interest from both the academic and industrial communities as a method for high-speed pipelining without the use of intermediate latching. Although high-performance IC technologies, pipelined RISC and DSP architectures, and sophisticated CAD tools have enabled and driven several recent demonstration circuits, significant challenges remain before wave-pipelining will be used extensively in commercial chips. In this forum, we discuss whether these challenges are surmountable, and if so, what are the techniques that will be needed both now and with future VLSI technologies

Keywords

VLSI; clocks; combinational circuits; delays; digital signal processing chips; logic CAD; reduced instruction set computing; CAD techniques; DSP architectures; RISC; VLSI; combinational circuits; gate delays; high-performance IC technologies; high-speed pipelining; wave-pipelining; Circuits; Clocks; Delay; Design automation; Digital signal processing chips; Latches; Logic design; Pipeline processing; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.409223

Filename

409223