Title :
RTL synthesis with physical and controller information
Author :
Xu, Min ; Kurdahi, Fadi J.
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Abstract :
The current technology advances towards deep submicron have made it indispensable to consider layout and controller effects during all phases of chip synthesis. This paper proposes a paradigm for incorporating such information when synthesizing an RTL design from a scheduled behavioral specification. Experimental results corroborate the fact that layout and controller effects on chip area and performance are significant and cannot be ignored
Keywords :
circuit CAD; high level synthesis; integrated circuit layout; RTL synthesis; chip synthesis; controller information; layout effects; physical information; scheduled behavioral specification; Algorithm design and analysis; Computer science; Design methodology; Hardware; High level synthesis; Logic design; Processor scheduling; Silicon; Space exploration; Time factors;
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7786-4
DOI :
10.1109/EDTC.1997.582374
