A data recovery method for high-speed serial communication based on FPGA

Nowadays, serial communication is used in many high-speed communication situations instead of parallel communication. In high-speed serial communications, data recovery is an important and difficult part, which directly determines the success or failure of communication. This paper presents a FPGA-based data recovery method for high-speed serial signal. First, each bit of serial signal is over-sampled by four times and synchronized, then the transition edges of signal is detected, and finally we select the optimal sampling points to recover out the data that is synchronized with the standard sampling clock. Experimental results show that this method ran well under the data transmission rate of 50Mbps.