• DocumentCode
    3435834
  • Title

    High-speed C-testable systolic array design for Galois-field inversion

  • Author

    Chih-Tsun Huang ; Wu, Chen-Wen

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • fYear
    1997
  • fDate
    17-20 Mar 1997
  • Firstpage
    342
  • Lastpage
    346
  • Abstract
    Systolic architectures for inversion in Galois field (GF(2m )) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation
  • Keywords
    VLSI; C-testable systolic array design; GF inversion; Galois-field inversion; VLSI implementation; bit-parallel implementation; counter-free extended Euclidean algorithm; high-speed systolic array design; inversion algorithm; modularity; testability; Arithmetic; Circuit testing; Counting circuits; Cryptography; Error correction; Galois fields; Polynomials; Routing; Systolic arrays; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    European Design and Test Conference, 1997. ED&TC 97. Proceedings
  • Conference_Location
    Paris
  • ISSN
    1066-1409
  • Print_ISBN
    0-8186-7786-4
  • Type

    conf

  • DOI
    10.1109/EDTC.1997.582380
  • Filename
    582380
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3435834