Built-in reseeding for serial BIST

Author

Al-Yamani, Ahmad A. ; McCluskey, Edward J.

Author_Institution

Stanford Univ., CA, USA

fYear

2003

fDate

27 April-1 May 2003

Firstpage

63

Lastpage

68

Abstract

Reseeding is used to improve fault coverage in BIST pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost, testing using automatic test equipment (ATE) makes it hard to test the circuit while in the system. In this paper, we present a technique for built-in reseeding. Our technique requires no storage for the seeds. The seeds are encoded in hardware. The seeds we use are deterministic so 100% fault coverage can be achieved. Our technique causes no performance overhead and does not change the original circuit under test. Also, the technique we present is applicable for transition faults as well as single-stuck-at faults. Built-in reseeding is based on expanding every seed to as many ATPG patterns as possible. This is different from many existing reseeding techniques that expand every seed into a single ATPG pattern. This paper presents the built-in reseeding algorithm together with a hardware synthesis algorithm and implementation.

Keywords

automatic test pattern generation; built-in self test; circuit simulation; fault location; integrated circuit design; integrated circuit technology; logic design; logic simulation; logic testing; random sequences; BIST built-in reseeding; BIST pseudo-random testing; deterministic seeds; fault coverage; hardware encoded seeds; multiple ATPG patterns; seed expansion; serial BIST; single-stuck-at faults; transition faults; Built-in self-test; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2003. Proceedings. 21st

ISSN

1093-0167

Print_ISBN

0-7695-1924-5

Type

conf

DOI

10.1109/VTEST.2003.1197634

Filename

1197634