VHDL extensions for complex transmission line simulation

Author

Walker, Peter ; Ghosh, Sumit

Author_Institution

Div. of Eng., Brown Univ., Providence, RI, USA

fYear

1997

fDate

17-20 Mar 1997

Firstpage

368

Lastpage

372

Abstract

This paper proposes extensions to the VHDL grammar and defines new semantics in the language to model the timing behavior of high frequency buses and clock lines with multiple, distinct taps in a VHDL description. The proposed language constructs utilize transmission line analysis to model the timing behavior but avoids the continuous time simulation by using line-events

Keywords

circuit analysis computing; computational linguistics; digital circuits; grammars; hardware description languages; timing; transmission line theory; VHDL description; VHDL extensions; VHDL grammar; complex transmission line simulation; digital buses; high frequency buses; high frequency clocks; semantics; timing behavior; transmission line analysis; Circuit simulation; Clocks; Conductors; Delay effects; Discrete event simulation; Hardware; Propagation delay; Space vector pulse width modulation; Timing; Transmission lines;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1997. ED&TC 97. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7786-4

Type

conf

DOI

10.1109/EDTC.1997.582384

Filename

582384

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3435925