Title :
VHDL extensions for complex transmission line simulation
Author :
Walker, Peter ; Ghosh, Sumit
Author_Institution :
Div. of Eng., Brown Univ., Providence, RI, USA
Abstract :
This paper proposes extensions to the VHDL grammar and defines new semantics in the language to model the timing behavior of high frequency buses and clock lines with multiple, distinct taps in a VHDL description. The proposed language constructs utilize transmission line analysis to model the timing behavior but avoids the continuous time simulation by using line-events
Keywords :
circuit analysis computing; computational linguistics; digital circuits; grammars; hardware description languages; timing; transmission line theory; VHDL description; VHDL extensions; VHDL grammar; complex transmission line simulation; digital buses; high frequency buses; high frequency clocks; semantics; timing behavior; transmission line analysis; Circuit simulation; Clocks; Conductors; Delay effects; Discrete event simulation; Hardware; Propagation delay; Space vector pulse width modulation; Timing; Transmission lines;
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7786-4
DOI :
10.1109/EDTC.1997.582384
