A low-power architecture for integrating analog-to-digital converters

This paper reports on a modified architecture for single-slope integrating analog-to-digital converter (ADC) for use in image sensors and biomedical or any other applications where the value of the input analog signal has small and slow variations. In this architecture, instead of digitizing every new analog sample independently, the difference of the new sample with the previous sample is digitized. This idea will therefore considerably reduce the power consumption of the ADC. In order to illustrate the effectiveness of the proposed idea, an 8- bit, 4 kS/s ADC is designed and simulated in a 0.18 ¿m CMOS technology. The proposed ADC is very power efficient when the input signal is very slow and has a small variation in voltage amplitude. Simulations confirm that the proposed ADC architecture shows more than 80% power saving compared to conventional architecture for an input signal amplitude of 0.2V_FS.