DocumentCode
3435958
Title
Exploiting temporal independence in distributed preemptive circuit simulation
Author
Walker, Peter ; Ghosh, Sumit
Author_Institution
Div. of Eng., Brown Univ., Providence, RI, USA
fYear
1997
fDate
17-20 Mar 1997
Firstpage
378
Lastpage
382
Abstract
In digital circuit simulation hidden opportunities for concurrent execution of models often exist, arising from the propagation delay associated with the generation of output events by the circuit models. An event prediction algorithm is developed to identify such parallelism, increasing the simulation execution rate. The algorithm uses an event prediction network and simulates circuits asynchronously and deadlock free, while honoring the preemptive semantics associated with digital circuit simulation
Keywords
asynchronous circuits; circuit analysis computing; delays; discrete event simulation; logic CAD; asynchronous simulation; concurrent execution; digital circuit simulation; distributed preemptive circuit simulation; event prediction algorithm; output events; preemptive semantics; propagation delay; simulation execution rate; temporal independence; Circuit simulation; Clocks; Computational modeling; Concurrent computing; Delay; Digital circuits; Discrete event simulation; Parallel processing; Predictive models; System recovery;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location
Paris
ISSN
1066-1409
Print_ISBN
0-8186-7786-4
Type
conf
DOI
10.1109/EDTC.1997.582386
Filename
582386
Link To Document