Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression

Author

Bayraktaroglu, Ismet ; Orailoglu, Alex

Author_Institution

Test Technol. Group, Sun Microsystems, Sunnyvale, CA, USA

fYear

2003

fDate

27 April-1 May 2003

Firstpage

113

Lastpage

118

Abstract

A methodology for the determination of decompression hardware that guarantees complete fault coverage for a unified compaction/compression scheme is proposed. Test cube information is utilized for the determination of a near optimal decompression hardware. The proposed scheme attains simultaneously high compression levels and reduced pattern counts through a linear decompression hardware. Significant test volume and test application time reductions are delivered through the scheme we propose while a highly cost effective hardware implementation is retained.

Keywords

automatic test equipment; automatic test pattern generation; combinatorial mathematics; integrated circuit testing; logic testing; decompression hardware determination; fault coverage; linear decompression hardware; test application time; test cube information; test time reduction; test volume reduction; unified test pattern compaction/compression; Compaction; Computer science; Costs; Hardware; Moore´s Law; Pins; Sequential analysis; Sun; Test pattern generators; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2003. Proceedings. 21st

ISSN

1093-0167

Print_ISBN

0-7695-1924-5

Type

conf

DOI

10.1109/VTEST.2003.1197641

Filename

1197641