Fast power loss calculation for digital static CMOS circuits

Author

Gavrilov, S. ; Glebov, A. ; Rusakov, S. ; Blaauw, D. ; Jones, L. ; Vijayan, G.

Author_Institution

Acad. of Sci., Moscow, Russia

fYear

1997

fDate

17-20 Mar 1997

Firstpage

411

Lastpage

415

Abstract

In this paper we present a new dynamic power estimation method that produces accurate power measures at considerably faster run times. The approach uses an enhanced switch-level simulation algorithm that takes into account both short-circuit power and charge-sharing power effects. In benchmarks against a popular commercial power simulation tool, our approach yields power measurements on average within 3% of the commercial solution, while taking between 15 to 20 times less CPU time

Keywords

CMOS digital integrated circuits; circuit analysis computing; integrated circuit modelling; losses; charge-sharing; digital static CMOS circuit; dynamic power estimation; power loss; short-circuit; switch-level simulation algorithm; CMOS digital integrated circuits; CMOS logic circuits; Central Processing Unit; Circuit simulation; Delay estimation; Design optimization; Power measurement; Switches; Switching circuits; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1997. ED&TC 97. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7786-4

Type

conf

DOI

10.1109/EDTC.1997.582392

Filename

582392

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3436043