Title :
Fast power loss calculation for digital static CMOS circuits
Author :
Gavrilov, S. ; Glebov, A. ; Rusakov, S. ; Blaauw, D. ; Jones, L. ; Vijayan, G.
Author_Institution :
Acad. of Sci., Moscow, Russia
Abstract :
In this paper we present a new dynamic power estimation method that produces accurate power measures at considerably faster run times. The approach uses an enhanced switch-level simulation algorithm that takes into account both short-circuit power and charge-sharing power effects. In benchmarks against a popular commercial power simulation tool, our approach yields power measurements on average within 3% of the commercial solution, while taking between 15 to 20 times less CPU time
Keywords :
CMOS digital integrated circuits; circuit analysis computing; integrated circuit modelling; losses; charge-sharing; digital static CMOS circuit; dynamic power estimation; power loss; short-circuit; switch-level simulation algorithm; CMOS digital integrated circuits; CMOS logic circuits; Central Processing Unit; Circuit simulation; Delay estimation; Design optimization; Power measurement; Switches; Switching circuits; Threshold voltage;
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7786-4
DOI :
10.1109/EDTC.1997.582392
