Title :
An efficient test relaxation technique for synchronous sequential circuits
Author :
El-Maleh, Aiman ; Al-Utaibi, Khaled
Author_Institution :
King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
fDate :
27 April-1 May 2003
Abstract :
Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester Relaxing test sequences can improve the efficiency of both test compression and test compaction. In addition, the relaxation process can identify self-initializing test sequences for synchronous sequential circuits. In this paper we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.
Keywords :
data compression; fault diagnosis; integrated circuit testing; logic testing; sequential circuits; system-on-chip; SOC; circuit under test; fault coverage; memory requirements; self-initializing test sequences; synchronous sequential circuits; systems-on-a-chip; test compaction; test compression; test relaxation technique; total testing time; Automatic testing; Circuit faults; Circuit testing; Compaction; Integrated circuit testing; Sequential analysis; Sequential circuits; System testing; System-on-a-chip; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 2003. Proceedings. 21st
Print_ISBN :
0-7695-1924-5
DOI :
10.1109/VTEST.2003.1197649