DocumentCode
3436261
Title
Efficient seed utilization for reseeding based compression [logic testing]
Author
Volkerink, Erik H. ; Mitra, Subhasish
Author_Institution
Center for Reliable Comput., Stanford Univ., CA, USA
fYear
2003
fDate
27 April-1 May 2003
Firstpage
232
Lastpage
237
Abstract
The conventional LFSR reseeding technique for test data compression generates one test pattern from each LFSR seed. The seed size is determined by the maximum number of specified bits in a test pattern belonging to a given test set. However, for most practical designs the majority of test patterns have significantly fewer specified bits compared to the maximum. This limits the amount of compression that can be achieved with conventional reseeding. This paper presents a new reseeding technique that overcomes this problem by generating a single test pattern from multiple seeds and multiple test patterns from a single seed. The new reseeding technique is applied to two industrial designs, resulting in significant reduction in tester memory requirement and test application time compared to the conventional reseeding technique.
Keywords
automatic test pattern generation; data compression; integrated circuit design; integrated circuit testing; logic design; logic testing; shift registers; ATPG; LFSR reseeding technique; linear feedback shift register; logic testing; maximum specified bit number; reseeding based compression; seed size; seed utilization efficiency; test application time reduction; test data compression; test pattern generation; tester memory requirement reduction; Automatic test pattern generation; Bandwidth; Cyclic redundancy check; Flip-flops; Hardware; Laboratories; Linear feedback shift registers; Test data compression; Test pattern generators; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2003. Proceedings. 21st
ISSN
1093-0167
Print_ISBN
0-7695-1924-5
Type
conf
DOI
10.1109/VTEST.2003.1197656
Filename
1197656
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