Title :
Detecting intra-word faults in word-oriented memories
Author :
Hamdioui, Said ; De Goor, Ad J. ; Rodgers, Mike
Author_Institution :
Intel Corp., Santa Clara, CA, USA
fDate :
27 April-1 May 2003
Abstract :
This paper improves upon the state of the art in testing word oriented memories. It first presents a complete set of fault models for intra-word coupling faults. Then, it establishes the data background sequence (DBS) for each intra-word coupling fault. These DBSs will be compiled into a (1 + 28 * [log2B]) * n/B test with complete fault coverage of the target faults, where n is the size of the memory and B the word size. The test length can be reduced to 29 * n/B when the intra-word faults are restricted to physical adjacent cells within a word.
Keywords :
fault diagnosis; integrated circuit testing; integrated memory circuits; logic testing; random-access storage; complete fault coverage; data background sequence; fault models; intra-word coupling faults; intra-word fault detection; word oriented memory testing; Bills of materials; Educational institutions; Fault detection; Information technology; Laboratories; Random access memory; Read-write memory; Satellite broadcasting; System testing; Systems engineering and theory;
Conference_Titel :
VLSI Test Symposium, 2003. Proceedings. 21st
Print_ISBN :
0-7695-1924-5
DOI :
10.1109/VTEST.2003.1197657
