Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test

Demand for highly mobile and lower form-factor designs is driving semiconductor industry towards lower and lower power envelopes even for complex SOCs. With performance targets being expected to grow with every advancement in process technology, it becomes very difficult to achieve low power targets especially with shrinking geometries resulting in more pronounced second order effects in devices and interconnect. This tutorial is intended to cover some key challenges and best practices of design, verification and test domains for high performance ICs in low power space. First section starts off by explaining the basic trade-off between performance and power followed by how margins are used in various phases of design and analysis for better predictability of silicon behavior. It then covers the need for custom designs which could impact time-to-market but cannot be avoided due to the tighter and tighter specs on power and performance with every technology shift. This section concludes by discussing the impacts of overdesign and how they can be alleviated with some good practices during design phase. Second section covers the challenges involved in SOC-level and system-level verification of such high-performance designs with increased percentage of mixed-signal IP in them. It talks about some specific IPs and how to handle complex interactions between analog and digital domains there. It then covers the trade-off seen between speed and accuracy and associated best practices; and also covers some other common challenges like port order mismatches, etc. The final section addresses the challenge of testing the high performance designs especially given the process and design variability. For a long time semiconductor yield has been limited by random particle based issues and accordingly testing was geared towards detecting such defects. However, at feature sizes 65nm and below and with increased shift towards squeezing performance and power, systematic and process varia- ility issues have begun to contribute significantly towards the yield fallout. In keeping up with this, testing has to adapt to be able to identify good devices from bad or not-so-good devices in the presence of variability. This section, after quickly summarizing the fundamentals will address advanced topics such as power-aware, timing-aware and variability aware test techniques and on-chip test structures and techniques that can be used to predict correlation between speed and power of the designs. The proposed tutorial quickly touches upon the basics to be of interest to students, new engineers and managers but primarily focuses on covering the key challenges seen across the industry today in design, verification and test phases of complex high performance SOCs in low power space. Since it covers multiple domains, the content should be of interest to a wide range of students, scholars and engineers.