Design and optimization of multi-level TAM architectures for hierarchical SOCs

Author

Iyengar, Vikram ; Chakrabarty, Krishnendu ; Krasniewski, Mark D. ; Kumar, Gopind N.

Author_Institution

IBM Microeletronics, Essex Junction, VT, USA

fYear

2003

fDate

27 April-1 May 2003

Firstpage

299

Lastpage

304

Abstract

Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimization flows that exploit recent advances in TAM design for flattened SOC hierarchies. Unlike prior methods that assume flat test hierarchies, the proposed methods are directly applicable to real-world design transfer models between the core vendor and the SOC integrator. Experimental results are presented for four ITC´02 SOC test benchmarks.

Keywords

circuit optimisation; circuit simulation; hierarchical systems; integrated circuit design; integrated circuit testing; logic design; logic simulation; logic testing; system-on-chip; TAM architectures; core vendor/SOC integrator transfer models; embedded cores; flattened SOC hierarchies; modular hierarchical SOC testing; multilevel TAM optimization; system-on-chip; test access mechanism; Benchmark testing; Computer architecture; Costs; Design engineering; Design optimization; Embedded computing; Logic testing; Microelectronics; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2003. Proceedings. 21st

ISSN

1093-0167

Print_ISBN

0-7695-1924-5

Type

conf

DOI

10.1109/VTEST.2003.1197667

Filename

1197667