• DocumentCode
    3436480
  • Title

    Testability of 2-level AND/EXOR circuits

  • Author

    Drechsler, Rolf ; Hengster, Harry ; Schafer, Horst ; Hartmann, Joachim ; Becker, Bernd

  • Author_Institution
    Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
  • fYear
    1997
  • fDate
    17-20 Mar 1997
  • Firstpage
    548
  • Lastpage
    553
  • Abstract
    It is often stated that AND/EXOR circuits are much easier to test than AND/OR circuits. This statement only holds for restricted classes of AND/EXOR expressions, like positive polarity Reed-Muller expressions and fixed polarity Reed-Muller expressions. For these two classes of circuits good deterministic testability properties are known. In this paper we show that for these circuits also good random pattern testability can be proven. An input probability distribution is given which yields a short expected test length for biased random patterns. This is the first time that theoretical results on random pattern testability have been presented for 2-level AND/EXOR circuit realizations of arbitrary Boolean functions. For more general classes of 2-level AND/EXOR circuits analogous results are not proven. We present experimental results that show that in general minimized 2-level AND/OR circuits are as well (or badly) testable as minimized 2-level AND/EXOR circuits
  • Keywords
    Boolean functions; Reed-Muller codes; built-in self test; combinational circuits; logic gates; logic testing; Boolean functions; biased random patterns; deterministic testability properties; expected test length; fixed polarity Reed-Muller expressions; input probability distribution; positive polarity Reed-Muller expressions; random pattern testability; restricted classes; testability; two-level AND/EXOR circuits; Automatic testing; Boolean functions; Built-in self-test; Circuit testing; Hardware; Minimization; Probability distribution; Software testing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    European Design and Test Conference, 1997. ED&TC 97. Proceedings
  • Conference_Location
    Paris
  • ISSN
    1066-1409
  • Print_ISBN
    0-8186-7786-4
  • Type

    conf

  • DOI
    10.1109/EDTC.1997.582415
  • Filename
    582415