On the use of reset to increase the testability of interconnected finite-state machines

We propose a DFT solution for synchronous sequential circuits described as interconnections of finite-state machines, that takes into account specific requirements for justification of test sequences and propagation of fault effects occurring during test generation. We present this solution in the context of the output sequence justification problem. The proposed DFT solution is based on the use of reset. Three types of reset mechanisms are considered, having increasing overhead and increasing flexibility. The third type allows every output sequence over the output alphabet of a machine to be justified