• DocumentCode
    3436552
  • Title

    An FFT core for DVB-T2 receivers

  • Author

    Turrillas, M. ; Cortés, A. ; Vélez, I. ; Sevillano, J.F. ; Irizar, A.

  • Author_Institution
    Dept. of Electron. & Commun., CEIT & Tecnun, San Sebastian, Spain
  • fYear
    2009
  • fDate
    13-16 Dec. 2009
  • Firstpage
    120
  • Lastpage
    123
  • Abstract
    This paper presents the design and implementation of a pipeline radix-25 SDF FFT core for DVB-T2 receivers. DVB-T2 operation needs 1K/2K/4K/8K/16K/32K multiple mode FFT processors. The radix-25 SDF architecture is a new and more efficient architecture, which has been optimized for implementing a multiple mode core. SNR results for different data and twiddle factor bitwidths are provided. Furthermore, the results of the FFT core implementation in an FPGA are presented.
  • Keywords
    digital video broadcasting; fast Fourier transforms; field programmable gate arrays; television receivers; DVB-T2 receivers; FFT processors; FPGA; SDF FFT core; SNR results; digital video broadcasting; fast Fourier Transform; twiddle factor bitwidths; Delay; Digital video broadcasting; Discrete Fourier transforms; Fast Fourier transforms; Flow graphs; HDTV; OFDM modulation; Pipelines; TV; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on
  • Conference_Location
    Yasmine Hammamet
  • Print_ISBN
    978-1-4244-5090-9
  • Electronic_ISBN
    978-1-4244-5091-6
  • Type

    conf

  • DOI
    10.1109/ICECS.2009.5410934
  • Filename
    5410934
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3436552