Improving diagnostic resolution of delay faults using path delay fault model

The known methods of transition fault diagnosis usually suffer from the drawback of many candidates. The method presented in this paper aims at reducing the number of suspects. The transition fault patterns were generated by Philips in-house ATPG tool and applied on the tester. The fail information from tester was subjected to fault diagnosis resulting in a small list of faulty candidates. We then injected the delay faults into the golden netlist of the test chip and confirmed through simulation whether or not their behavior matched with the tester results. Upon successful matching, we proceeded with the selection of few testable paths through the suspect faulty node and created corresponding path delay patterns using the path delay ATPG (a prototype at the University of Bremen, developed in cooperation with Philips Semiconductors GmbH, Hamburg). Finally, we verified those path delay patterns on the tester to increase the confidence level of the diagnosis method The experimental results show the effectiveness of our novel approach for improving diagnostic resolution.