Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model

Author

Manich, S. ; Figueras, J.

Author_Institution

Univ. Politecnica de Catalunya, Barcelona, Spain

fYear

1997

fDate

17-20 Mar 1997

Firstpage

597

Lastpage

602

Abstract

A methodology to find the couple of vectors maximizing the weighted switching activity in combinational CMOS circuits under variable delay model is presented. The weighted switching activity maximization problem is shown to be equivalent to a fault testing problem on a transformed circuit. A maximum weighted switching activity is achieved by test vectors covering a selected set of faults of the transformed circuit. Automatic Test and Pattern Generation tools are used to find the maximizing pair of vectors. The validity of the proposal is demonstrated on the ISCAS-85 benchmark circuits and the results show that the simulation time is reduced by an order of magnitude and the estimation of the maximum weighted switching activity is improved in comparison with pseudo-random sample simulation

Keywords

CMOS logic circuits; VLSI; circuit analysis computing; combinational circuits; delays; fault diagnosis; logic testing; ISCAS-85 benchmark circuits; combinational CMOS circuits; fault testing problem; maximization problem; maximum weighted switching activity; pseudo-random sample simulation; simulation time; test vectors; variable delay model; weighted switching activity; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Coupling circuits; Delay; Semiconductor device modeling; Switching circuits; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1997. ED&TC 97. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7786-4

Type

conf

DOI

10.1109/EDTC.1997.582422

Filename

582422