Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors

Author

Mallya, N.B. ; Patil, G. ; Raveendran, B.

Author_Institution

K.K. Birla Goa Campus, BITS Pilani, Zuarinagar, India

fYear

2015

fDate

3-7 Jan. 2015

Firstpage

65

Lastpage

70

Abstract

This paper proposes a novel cache architecture -- Way Halted Prediction -- to reduce energy consumption and effective access time of set associative caches. This is achieved with the help of halt tag array and prediction circuit. Experimental evaluation of various SPEC benchmark programs on CACTI 5.3 and CASIM simulators reveal that the proposed architecture offers 33%, 6% and 3% savings in dynamic energy consumption and 1.80%, 6.13% and -1.95% saving in effective access time over conventional, way predicting and way halting cache architectures respectively.

Keywords

cache storage; circuit simulation; content-addressable storage; embedded systems; energy consumption; microprocessor chips; CACTI 5.3 simulator; CASIM simulator; SPEC benchmark program; dynamic energy consumption; embedded processor; energy efficient cache architecture; halt tag array; halting cache architecture; prediction circuit; set associative cache; way halted prediction cache; Accuracy; Arrays; Benchmark testing; Decoding; Energy consumption; Energy efficiency; Program processors; cache architecture; energy efficient cache design; way halting; way predicting;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design (VLSID), 2015 28th International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Type

conf

DOI

10.1109/VLSID.2015.16

Filename

7031709