Title :
A circuit level fault model for resistive opens and bridges
Author :
Li, Zhuo ; Lu, Xiang ; Qiu, Wangqi ; Shi, Weiping ; Walker, D.M.H.
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
fDate :
27 April-1 May 2003
Abstract :
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are modeled. In this paper, we propose a circuit level model for resistive open and bridge faults. All possible fault behaviors are illustrated and a general resistive bridge delay calculation method is proposed. The new models are practical and easy to use. Fault simulation results show that the new models help the delay test to catch more bridge faults.
Keywords :
VLSI; delays; fault simulation; integrated circuit interconnections; integrated circuit testing; logic testing; VLSI; bridges; circuit level fault model; delay calculation method; delay faults; delay test; fault behaviors; interconnect; resistive opens; Bridge circuits; Circuit faults; Circuit simulation; Circuit testing; Delay effects; Fault detection; Integrated circuit interconnections; Integrated circuit testing; SPICE; Semiconductor device modeling;
Conference_Titel :
VLSI Test Symposium, 2003. Proceedings. 21st
Print_ISBN :
0-7695-1924-5
DOI :
10.1109/VTEST.2003.1197678
