DocumentCode :
3436737
Title :
Analyzing crosstalk in the presence of weak bridge defects
Author :
Irajpour, Shahdad ; Nazarian, Shahin ; Wang, Lei ; Gupta, Sandeep K. ; Breuer, Melvin A.
Author_Institution :
Dept. of EE - Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear :
2003
fDate :
27 April-1 May 2003
Firstpage :
385
Lastpage :
392
Abstract :
An extensive simulation study of various combinations of resistive bridges and crosstalk has been performed and several notable properties that have significant implications for test development have been discovered. Scenarios have been identified where a combination of a bridge at one site and a crosstalk at a separate site in its transitive fanout (or vice versa) can cause slowdown/speed-up whose magnitude significantly exceeds the sum of the slow-down/speed-up, caused by each effect in isolation. It has also been identified that a test vector generated for crosstalk may in fact be invalidated due to the presence of a weak bridge at the crosstalk site. The properties discovered, provide the motivation for a more analytical study that will eventually lead to the proposed framework for test development.
Keywords :
CMOS logic circuits; cellular arrays; crosstalk; logic simulation; logic testing; SCMOS cell library; crosstalk; resistive bridges; simulation study; test development; transitive fanout; weak bridge defects; Analytical models; Bridge circuits; Character generation; Circuit testing; Crosstalk; Inverters; MOSFETs; Performance analysis; Performance evaluation; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2003. Proceedings. 21st
ISSN :
1093-0167
Print_ISBN :
0-7695-1924-5
Type :
conf
DOI :
10.1109/VTEST.2003.1197679
Filename :
1197679
Link To Document :
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