Low voltage low power techniques in design of zero IF CMOS receivers

In this paper a new technique is proposed for designing the front-end of the narrow band CMOS receivers. The signal current of the input transconductance directly drives the low flicker noise PMOS switches of the mixer. Two inductors connected to VDD provide the DC current path for the input transconductance and the switches. The inductors absorb the parasitic capacitances of the switches at the operating frequency reducing the noise, and nonlinearity components at the output. Due to fewer transistors in stack the approach provides large signal swing at the output which makes it desirable for low voltage and low power applications. A low voltage technique is used for designing the CMFB circuit for stabilizing the common mode of the output. The output of the downconverter is a second order low pass passive filter comprising of series filtering and the usual parallel filtering. The series filtering not only relaxes the linearity of other subsequent stages but also; provides lead-lag compensation making the CMFB loop more stable. The techniques have been applied to a front-end of a prototype UMTS receiver in 0.18¿m CMOS technology using 1.2V supply voltage. The simulation results show 26.5 dB voltage conversion gain, -5.5 dBm IIP3, 51.5 dBm IIP2, -20.5 dBm 1 dB-CP, 3.1dB double side band thermal noise figure, and 6 kHz flicker noise corner frequency. The circuit only draws 4.5mA current from the 1.2V supply voltage.