A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager

Author

Uhlig, Johannes ; Schüffny, René ; Neubauer, Harald ; Hauer, Johann ; Haase, Joachim

Author_Institution

Dept. of Neural Circuits & Parallel VLSI-Syst., Univ. of Technol. Dresden, Dresden, Germany

fYear

2009

fDate

13-16 Dec. 2009

Firstpage

33

Lastpage

36

Abstract

This paper presents a novel ΣΔ-modified MASH architecture (MMA) for a CMOS imager. This architecture makes use of a 1st-order incremental continuous-time sigma-delta modulator with 1.5-bit internal quantizer. It shows key benefits regarding efficient decimation and reduced circuit complexity compared to conventional ΣΔ-architectures. Theory of operation, impact of non-idealities, implementation issues and benefits of the new architecture are depicted. The implementation of the MMA in an 180nm CMOS-Process and simulation results are presented.

Keywords

CMOS digital integrated circuits; sigma-delta modulation; 2nd-order-MASH ΣΔ-modulator; CMOS imager; low-power continuous-time incremental modulator; sigma-delta modulator; size 180 nm; CMOS integrated circuits; CMOS technology; Circuit simulation; Complexity theory; Delta-sigma modulation; Design automation; Image converters; Integrated circuit technology; Multi-stage noise shaping; Paper technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on

Conference_Location

Yasmine Hammamet

Print_ISBN

978-1-4244-5090-9

Electronic_ISBN

978-1-4244-5091-6

Type

conf

DOI

10.1109/ICECS.2009.5410946

Filename

5410946