DocumentCode
3436943
Title
Design of partially parallel scan chain
Author
Higami, Yoshinobu ; Kinoshita, Kozo
Author_Institution
Dept. of Appl. Phys., Osaka Univ., Japan
fYear
1997
fDate
17-20 Mar 1997
Firstpage
626
Abstract
This paper presents a design-for-testability technique, called partially parallel scan chain (PPSC), which aims at reduction of test length for sequential circuits. Since the partially parallel scan chain allows to control and observe subset of flip-flops (FFs) concurrently during scan shift operations, the number of scan shift clocks is reduced
Keywords
design for testability; flip-flops; logic design; logic testing; sequential circuits; design; design for testability; flip-flop; partially parallel scan chain; scan shift clock; sequential circuit; test length; Benchmark testing; Circuit faults; Circuit testing; Clocks; Fault detection; Flip-flops; Notice of Violation; Physics; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location
Paris
ISSN
1066-1409
Print_ISBN
0-8186-7786-4
Type
conf
DOI
10.1109/EDTC.1997.582439
Filename
582439
Link To Document