DocumentCode
3436981
Title
Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs
Author
Das, S. ; Kapoor, H.K.
Author_Institution
Dept. of CSE, Indian Inst. of Technol., Guwahati, Guwahati, India
fYear
2015
fDate
3-7 Jan. 2015
Firstpage
141
Lastpage
146
Abstract
Multicore processors have proliferated several domains ranging from small scale embedded systems to large data-centers, making tiled CMPs (TCMP) the essential next generation scalable architecture. More processors need proportionally large cache to support the concurrent applications. NUCA architectures help in managing the capacity and access time for such larger cache designs. Static NUCA (SNUCA) has a fixed address mapping policy whereas dynamic NUCA (DNUCA) allows blocks to relocate nearer to the processing cores at runtime. The DNUCA architectures are well explored for systems with centralized cache banks and having processors along the periphery. SNUCA is well understood and explored for tiled CMPs whereas the same is not the case for DNUCA. Towards exploring various implementations of DNUCA for tiled CMPs, this paper presents an architecture along with migration and replacement policies for tiled CMPs. Experimental results show improvements with respect to TCMP based SNUCA. We discuss the differences and challenges of TCMP based DNUCA compared to original DNUCA, and present results for different configurations of migration and replacement policies. Simulation results shows improvements over TCMP based SNUCA by 44.7% and 9.6% in terms of miss-rate and cycles per instruction (CPI) respectively.
Keywords
cache storage; memory architecture; microprocessor chips; multiprocessing systems; CPI; DNUCA architectures; SNUCA; TCMP; cache designs; centralized cache banks; chip multiprocessor; concurrent applications; cycles per instruction; dynamic NUCA; fixed address mapping policy; large data-centers; migration policies; miss-rate; multicore processors; next generation scalable architecture; replacement policies; small scale embedded systems; static NUCA; tiled CMP; Benchmark testing; Computer architecture; Power system faults; Power system protection; Program processors; System-on-chip; Very large scale integration; Block migration; CMP; Dynamic NUCA; Last Level Cache; NUCA; Tiled-CMP;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design (VLSID), 2015 28th International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Type
conf
DOI
10.1109/VLSID.2015.29
Filename
7031722
Link To Document