Title :
2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids
Author :
Salodkar, N. ; Rajagopalan, S. ; Bhattacharya, S. ; Batterywala, S.
Author_Institution :
Samsung Res. Inst., Bangalore, India
Abstract :
Traditionally, automatic design rule correction (DRC) problem is modeled as a linear program with technology rules and design intents modeled as difference constraints under a minimum perturbation objective. However, these linear programs are often infeasible due to conflicts arising from rules and intents, lack of space or due to incomplete modeling. It is then required to identify problematic constraints and either dilute or drop them to make the linear program feasible. In presence of uniform grid and only difference type constraints, a weighted constraint graph is constructed and infeasibilities are detected as positive cycles. However, this approach breaks down in presence of multiple layer specific grids or discrete track patterns. In this paper, we suggest a novel method for Infeasible Constraint Set Identification (ICSI) for such layouts. Our method transforms the constraint set into a Boolean implications set. Since each implication has only two variables, solving the ICSI problem amounts to determining 2-Satisfiability of the implications set. We then suggest various strategies to resolve infeasibilities.
Keywords :
Boolean functions; computability; integrated circuit layout; logic design; 2SAT based infeasibility resolution; Boolean implications set; ICSI; design rule correction; discrete track patterns; infeasible constraint set identification; multiple layer specific grids; Algorithm design and analysis; Geometry; Layout; Shape; Transforms; Vectors; Very large scale integration; DRC; VLSI; grid;
Conference_Titel :
VLSI Design (VLSID), 2015 28th International Conference on
Conference_Location :
Bangalore
DOI :
10.1109/VLSID.2015.37