Neutron-induced latchup in SRAMs at ground level

Author

Dodd, Paul E. ; Shaneyfelt, Marty R. ; Schwank, James R. ; Hash, Gerald L.

Author_Institution

Sandia Nat. Lab., Albuquerque, NM, USA

fYear

2003

fDate

30 March-4 April 2003

Firstpage

51

Lastpage

55

Abstract

Neutron-induced single-event latchup has been studied in SRAMs manufactured by several different vendors. These SRAMs span different cell designs (six-transistor and four-transistor cells), technology generations (0.25 μm to 0.14 μm) and power supplies (5 V to 1.5 V). While some technologies appear to be latchup-free in neutron environments, others have neutron-induced latchup failure-in-time (FIT) rates as high as 300 FIT/Mbit at room temperature and maximum rated voltage. Latchup FIT rates increase dramatically with temperature. The observed latchup rates can lead to very high failure rates in systems with large amounts of memory, and cannot be circumvented using error correction.

Keywords

CMOS memory circuits; SRAM chips; failure analysis; integrated circuit reliability; integrated circuit testing; neutron effects; 0.25 to 0.14 micron; 5 to 1.5 V; CMOS SRAMs; SER; error correction; four-transistor cells; ground level; hard errors; maximum rated voltage; neutron-induced latchup failure-in-time rates; neutron-induced single-event latchup; power supplies; room temperature; single-event latchup; single-event upset; six-transistor cells; soft errors; technology generations; terrestrial cosmic rays; Cosmic rays; Error correction; Laboratories; Neutrons; Power generation; Power supplies; Random access memory; Silicon on insulator technology; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197720

Filename

1197720