Taper pad design to improve electrical performance of BGAs on wafer level package (WLP)

A taper pad design is proposed to improve signal integrity in the transition from traces on chip site to PCB. Transmission loss of the transition incorporating traces, taper pads, solder balls, and microstrip line is simulated through electromagnetic simulation tool. Compared with the conventional pad design, the proposed pad design has 2 dB of improvement and only 0.9 dB insertion loss at 40 GHz. In addition, its DC/AC parasitic resistance and AC parasitic inductance are extracted and proved to have 85/65 % and 19 % of reduction, respectively, against the conventional pad design. Finally, the design guide of the proposed pad design is presented to enhance the signal integrity of WLP.