• DocumentCode
    3437191
  • Title

    A Novel CKE-ODT-CSN Encoding Scheme in DDR Memory Interface

  • Author

    Murugan, V.I. ; Mayandi, N. ; Arul, S.

  • Author_Institution
    Syst. Design Eng., Rambus Chip Technol., Bangalore, India
  • fYear
    2015
  • fDate
    3-7 Jan. 2015
  • Firstpage
    204
  • Lastpage
    208
  • Abstract
    In the continuous evolution of DRAM technologies and increased pin count, the paper outlines the roadblocks faced in adding new pins and presents a novel coding approach for elimination of pins in DDR memory interface. The paper targets CSN, CKE and ODT pins of DRAM and presents a coding algorithm where all the mentioned pins´ information is encoded and transferred to the DRAM on only two pins against the original three. The encoding and decoding blocks are discussed across both single data rate and double data rate DDR CA topology. The paper concludes by explaining the importance of the encoding algorithm and the additional features which can be supported through the coding scheme.
  • Keywords
    DRAM chips; encoding; CKE-ODT-CSN encoding; DDR memory interface; DRAM; clock enable-on die termination-chip select encoding; coding algorithm; double data rate DDR CA topology; pin elimination; single data rate DDR CA topology; Clocks; Decoding; Delays; Encoding; Pins; Random access memory; Topology; Chip Select (CSN); Clock Enable (CKE); DDR memory; On Die Termination (ODT); pin-elimination;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design (VLSID), 2015 28th International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Type

    conf

  • DOI
    10.1109/VLSID.2015.40
  • Filename
    7031733