Title :
A new I/O signal latchup phenomenon in voltage tolerant ESD protection circuits
Author :
Salcedo-Suñer, Jorge ; Cline, Roger ; Duvvury, Charvaka ; Cadena-Hernandez, Alfonso ; Ting, Larry ; Schichl, Joe
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
fDate :
30 March-4 April 2003
Abstract :
We report for the first time a new type of unexpected latch-up phenomenon that can occur in deep sub-micron technologies with the required implementation of voltage tolerant ESD protection circuits. In contrast to the well known Standard latchup, this new latchup, dubbed Signal Latchup, becomes evident only through the interaction from neighboring I/O pins. The issues involved with this latchup effect and the subsequent trade-off with ESD are presented in detail. A new latchup specification is also proposed.
Keywords :
CMOS integrated circuits; electrostatic discharge; failure analysis; integrated circuit layout; integrated circuit reliability; protection; I/O signal latchup phenomenon; deep submicron technologies; failure mode; latchup specification; layout comparison; signal latchup; voltage tolerant ESD protection circuits; CMOS technology; Circuits; Condition monitoring; Diodes; Electrostatic discharge; Pins; Power supplies; Protection; Thyristors; Voltage;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International
Print_ISBN :
0-7803-7649-8
DOI :
10.1109/RELPHY.2003.1197725
