An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation ADC in 0.18µm CMOS

An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation (SA) analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 μm digital process is presented. To overcome the input sampling switches limitation imposed by the low supply voltage we make use of a track-and-hold circuit based on a low-voltage, low-stress and reliable clock signal with a novel rail-to-rail track-and-latch comparator circuit. Power and area saving are achieved using splitarray charge redistribution-based SA ADC. Successive approximation and control logic is implemented using a robust single clock phase D flip-flop. Preliminary simulation results show that the ADC consumes only 3.68 μW.