Ultra-fast Cap-less LDO for Dual Lane USB in 28FDSOI

Author

Singh, S.K. ; Kanungo, G.D.

Author_Institution

PIMSD, STMicroelectron., Noida, India

fYear

2015

fDate

3-7 Jan. 2015

Firstpage

254

Lastpage

259

Abstract

A fully on-chip LDO for very fast load transient up to 15mA/nsec in 28nm FDSOI is presented. Proposed LDO capitalizes on technological boost given to on-chip capacitance density and MOS current drives to implement conventional compensation technique without using off-chip capacitor. Dominant output pole enables the LDO to achieve its superior load transient performance. Proposed LDO generates 1.0V output from a 1.6V input supply and has maximum output current capacity of 15mA. Simulated worst case PSR at 10kHz is-23dB and current efficiency is 93% at maximum load condition. Three such LDOs are combined to provide dedicated 1.0V supplies to dual lane USB cores and their PLL. Area including reference generator, three LDO and all on-chip capacitances is 0.2mm2.

Keywords

peripheral interfaces; phase locked loops; silicon-on-insulator; voltage regulators; 28FDSOI; MOS current; PLL; current 15 mA; dominant output pole; dual lane USB core; low dropout regulator; on-chip capacitance density; reference generator; ultrafast capacitor-less LDO; voltage 1 V; voltage 1.6 V; voltage regulators; Capacitance; Capacitors; Logic gates; Regulators; System-on-chip; Transient analysis; Universal Serial Bus; CMOS; FDSOI; LDO; PSRR; fully on-chip voltage regulators; linear voltage regulators; voltage regulators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design (VLSID), 2015 28th International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Type

conf

DOI

10.1109/VLSID.2015.49

Filename

7031742